Dr Stoyan Stoyanov

Reader

Stoyan Stoyanov joined the University in 1999.

Expertise and Collaborations

  1. Research interests and expertise in computational engineering (finite element analysis, CFD, multi-physics), Design-for-X for electronic products, design optimisation, robustness validation & engineering reliability
  2. Development and integration of numerical techniques for CAE in microelectronics, micro-systems, embedded devices, etc.
  3. Worked extensively on the award winning Cutty Sark project
  4. Collaborated with 20+ companies including Philips, BAE Systems, BOC, Photonics, TRW Automotive, Celestica, DEK, Cutty Sark Trust, GSK, etc and leading academic organisations (Cambridge, Nottingham, Loughborough, Heriot-Watt, Technical University of Dresden, City University Hong Kong, and others)

Qualifications

  1. NVQ Level 4 in Management, 09/2004-09/2006, CMI, Certified 02/2008
  2. PhD, University of Greenwich, Title: Optimisation Modelling for Microelectronics Product Design (2004)
  3. MSc in Applied Mathematics, Operational Research and Optimisation, Sofia University, Bulgaria (1996)

Responsibilities within the university

(1) Co-managing CMRG
(2) Support for project proposals and bids
(3) Member of the University of Greenwich Peer Review College since 2012
(4) Member of the review panel at the University of Greenwich for the RESEARCH AND ENTERPRISE INVESTMENT PROGRAMME

Course leader 2016/17

Reliability and Optimisation 

Selected publications

Over 60 conference and journal publications including four chapters in books.

Awards

1) Awarded Readership in 2010

2) Winner of the National Times Higher Education Award 2009 for Outstanding Engineering Research Team of the Year (October 2009)

3) Knowledge Base Collaboration Award, and the overall "champion" award, the Knowledge Transfer Collaboration of 2008, at the London Knowledge Transfer Awards run by London Development Agency (December 2008

4) The University of Greenwich 2008 Early Career Research Excellence Award

5) Best Partnership Award at the National Technology Strategy Board (TSB) 2008 KTP awards (March 2008)

6) Excellent Presentation Award at the 33rd International Spring Seminar on Electronics Technology for the paper "Reduced Order Modelling for Risk Mitigation in De3sign of Miniaturised/Integrated Products" (May 2010, Warsaw, Poland

7) A certificate for recognising significant contribution to organisation of IEEE 2nd International ESTC, from president of IEEE CPMT society (2008)

8) Best paper award at the Fourth IEEE International Symposium on Electronic Packaging Technology (ISEPT), Beijing, China, for the work entitled "A modelling and experimental analysis of the no-flow underfill process for flip-chip assembly"

Recognition

Member of Institute of Electrical and Electronics Engineers (IEEE);

Member of Computational Intelligence Society;

Member of Components, Packaging, & Manufacturing Technology(CPMT) Society;

Member of the Steering Committee of the International Spring Seminar on Electronics Technology

Research / Scholarly interests

Numerical modelling and simulation

Design optimisation

Robustness Validation

Engineering reliability

Statistical data analysis

Prognostics and Health Management

Key funded projects

Research Project: Technology Assessment on the Effects of Refinishing Lead-Free Microelectronic Components (DoD Funding)

Stage 1.5+ : 06/2012-03/2013

Stage 1.5 : 10/2011-04/2012

Stage 1.0 : 10/2010-09/2011

Partners: Micross Components Limited, Selex Galileo, Rolls Royce, General Dynamics, Cassidian, CMCA, Scimus Solutions, Senelac Ltd, and Unisem Europe

Description Stage 1.5+: Thermo-mechanical Modelling of the impact of Hot Solder Dip refinishing process, Laser de- and re-balling approach to refinishing BGA components, BGA thermo-mechanical response to reflow assembly process and behaviour of 1st level solder interconnects, reliability assessment for satellite application

Description Stage 1.5: Thermo-mechanical modelling and limited experimental assessment of the impact of refinishing leadless components (BGAs, QFNs) using Micross Components' double hot solder dip process. 

Description Stage 1.0: Modelling and experimental assessment of the impact of refinishing leaded components (QFP, SOP, etc) using using Micross Components' double hot solder dip process. The study of this post-manufacturing process aimed at assessing the potential risk of damage due to Hot Solder Dip (HSD)process. This process is one of the risk mitigation strategies to the tin whisker phenomenon that imposes serious risk of electronics components failure in high reliability applications.